The invention relates to computer systems, and more particularly to integrated bus bridge designs for use in high performance computer systems.
Computer architectures generally include a number of devices interconnected by one ore more buses. For example, conventional computer systems typically include a CPU coupled through bridge logic to an external memory. A main memory controller is thus incorporated within the bridge logic to generate various control signals for accessing the main memory. An interface to a high bandwidth local expansion bus, such as the Peripheral Component Interconnect (PCI) bus, may be included as a portion of the bridge logic. Examples of devices which can be coupled to the local expansion bus comprise network interface cards, audio processors, IDE controllers, and so forth.
However, conventional bridge logic provides relatively poor performance with respect to main memory accesses by other devices residing on peripheral buses, and similarly provides relatively poor performance with respect to data transfers between the CPU and peripheral buses as well as between peripheral devices interconnected by the bridge logic. In recent years, computer systems have been increasingly utilized in the processing of various real time applications, including multimedia applications such as video and audio, telephony, and speech recognition. These systems require not only that the CPU have adequate access to the main memory, but also that devices residing on various peripheral buses such as the PCI bus have fair access to the main memory. Furthermore, it is often important that transactions between processor bus and peripheral buses should be efficiently handled. The bus bridge logic for a modern computer system must accordingly include mechanisms to efficiently prioritize and arbitrate among the varying requests of devices seeking access to main memory and to other system components coupled through the bridge logic.
To support high performance, many bus bridge designs support write posting operations for write transactions originating on one or more of the interfaced buses. Specifically, many bus bridge designs allow the bus bridge to receive and “post” a write transaction originating on the processor bus or the peripheral bus. When the write data is received by the bus bridge, the transaction on the processor or peripheral bus can be completed, even though the write data has not yet actually been written into main memory or to a destination bus by the bus bridge. Once a write has been posted in the bus bridge, the bridge may complete the write to the destination at a later time in an efficient manner without stalling the initial write transaction presented on the processor or peripheral bus.
While write posting in bus bridges greatly improves performance, problems relating to memory coherency can arise. To avoid coherency problems, various ordering rules may be established. The PCI Local Bus Specification specifies the ordering requirements for bus bridges. For example, one of the ordering requirements states that posted memory writes originating on the opposite side of the bridge from a read transaction and completing on the read-destination bus before the read command completes on the read-transaction bus must complete on the read-origin bus in the same order. In other words, before the read transaction can complete on its originating bus, it must pull out of the bridge any posted writes that originated on the opposite side and were posted before the read command completes on the read-destination bus. Yet the ordering requirements are so strict that it discourages further improvement in system performance. In practice, the read completion can be expedited on condition that the read command is not destined to the same master originating the posted memory write. Only if the read destination and the originating master are the same device must the above ordering rule be enforced. Therefore, it is desirable to provide a mechanism within a bus bridge to facilitate read completion even though there are outstanding write requests.